1. Field of the Invention
The present invention relates generally to methods of thin film deposition and, more specifically, to a method of minimizing structure overhang during the process of filling high aspect ratio gaps on substrates.
2. Background of the Invention
As semiconductor technology advances, circuit elements and interconnections on wafers or silicon substrates become increasingly more dense. In order to prevent unwanted interactions between these circuit elements, insulator-filled gaps or trenches located therebetween are provided to physically and electrically isolate the elements and conductive lines. However, as circuit densities continue to increase, the widths of these gaps decrease, thereby increasing gap aspect ratios, typically defined as the gap height divided by the gap width. As a result, filling these narrower gaps becomes more difficult, which can lead to unwanted voids and discontinuities in the insulating or gap-fill material.
In previous generations of microelectronic devices the gaps between metal lines were filled using either PECVD (plasma enhanced chemical vapor deposition) processes or the combinations of those with sputter etch steps. For example, U.S. Pat. No. 5,270,264 to Andideh et al. describes a gap-filling process which involves the steps of deposition by PECVD, followed by argon sputter etching, followed by another PECVD deposition step, i.e., a PECVD xe2x80x9cdep-etch-depxe2x80x9d process. The article by S. Pennington et al. (hereinafter xe2x80x9cthe article by Pennington et al.xe2x80x9d), entitled xe2x80x9cAn Improved Interlevel Dielectric Process for Submicron Double-Level Metal Products,xe2x80x9d in Proceedings of the 6th International IEEE VLSI Multilevel Interconnection Conference, (1989), pp. 355-359, describes a dielectric gap-filling process using both PECVD and thermal CVD (THCVD). The article by D. Cote et al. (hereinafter xe2x80x9cthe article by Cote et al.xe2x80x9d), entitled xe2x80x9cLow-Temperature Chemical Vapor Deposition Processes and Dielectrics for Microelectronic Circuit Manufacturing at IBMxe2x80x9d, in the IBM Journal of Research and Development, vol. 39, no. 4, (July 1995), pp. 437-464, describes several known CVD processes, including low pressure (LP), atmospheric pressure (AP) CVD, and plasma-enhanced (PE) CVD, which are background to the present invention. However, the gap-fill capabilities of such processes or combinations of processes do not extend beyond aspect ratios of 1.3:1 at spacing 0.45 xcexcm or 4500 xc3x85, even when xe2x80x9cdep-etch-depxe2x80x9d cycles are performed, as described in U.S. Pat. No. 5,270,264 and the article by Cote et al. Specifically, the article by Cote et al. refers to and presents data demonstrating the inability of PECVD processes to satisfy the gap-fill requirements of advanced microelectronic devices with either undoped or doped silica glass.
In the gap-fill process described in U.S. Pat. No. 5,270,264, a step of deposition by PECVD is followed by a sputter etch step with argon and another step of deposition by PECVD. As understood by those skilled in the art, deposition by PECVD is strictly a deposition step, i.e., not involving simultaneous etching during exposure to the depositing plasma. U.S. Pat. No. 5,270,264 describes a gap-filling process which performs a sputter etch using inert gases of heavy atomic weight such as Ar, Kr, and Xe. The process parameters for the PECVD deposition and etching are specified in that patent for the plasma power density and pressure. In addition, the capabilities of the dep-etch-dep processes described in the articles by Pennington et al., by Cote et al., and U.S. Pat. No. 5,270,264 are limited by virtue of the use of PECVD deposition, the selection of sputter gases described therein, and the process parameters defined for the sputter etch step. As a result, the processes described in these references cannot be used to fill gaps having aspect ratios greater than about 2:1 and width less than about 0.65 xcexcm (6500 xc3x85).
High density plasma (HDP) chemical vapor deposition (CVD) processes are currently used to fill gaps having aspect ratios of about 3:1 and having close spacing, e.g. about 0.25 xcexcm. HDP processes operate at a pressure regime several (e.g., two to three) orders of magnitude lower than that of their PECVD counterparts. Moreover, in an HDP reactor, power is coupled inductively to the plasma, resulting in higher plasma density. Consequently, in an HDP reactor, because of the pressure and plasma characteristics, the species impinging on the depositing film surface are much more energetic than in a PECVD reactor, such that gas-solid collisions may result in sputtering of the deposited film. In an HDP CVD deposition process, the sputter etch component is typically between 10% and 20% of the net deposition rate. Another characteristic of HDP deposition is that increased bias power applied to the wafer results in an increased in-situ sputter etch component, thereby decreasing the deposition rate.
By contrast, in PECVD reactors the coupling is capacitive, resulting in much lower plasma density. The combination of low plasma density and high pressure results in negligible film sputtering in PECVD deposition. In addition, those skilled in the art will understand that the rate of film deposition in PECVD processes may increase with the amount of bias power applied to the wafer.
The differences in the physics and chemistry of PECVD and HDP processes result in significant differences in the growth of the deposited film. In PECVD processes, plasma is used to generate deposition precursors, which in turn, are driven to the wafer surface by applied bias to the wafer. Because of the relatively high pressure of operation (on the order of 1 Torr), the ions experience a large number of collisions as they cross the sheath. As a result, the flux of deposition precursor species to the wafer surface is distributed. Moreover, the mixture is depleted of deposition precursors as it diffuses towards the bottom of the trench, and, as a result, the net rate of film growth at the bottom of the trench is smaller than that at the entry region of the trench. Therefore, void-free filling of gaps having high aspect ratios (i.e., aspect ratios approaching or exceeding 2:1 at 0.65 xcexcm spacing) cannot be achieved using PECVD methods since the opening to the gap will be closed long before the gap is filled. For these reasons, the process sequence described in U.S. Pat. No. 5,270,264 of PECVD deposition, argon sputter etch, followed by another PECVD deposition, cannot provide void-free filling of high aspect ratio gaps at current microelectronic dimensions.
Existing HDP deposition processes typically employ chemical vapor deposition (CVD) with a gas mixture containing oxygen, silane, and inert gases, such as argon, to achieve simultaneous dielectric etching and deposition. In an HDP process, RF bias is applied to a wafer substrate in a reaction chamber. As a result, the flux of deposition precursors is perpendicular to the wafer, and the net film growth occurs perpendicularly to the bottom of the feature. Some of the gas molecules (particularly argon) are ionized in the plasma and accelerate toward the wafer surface when the RF bias is applied to the substrate. Material is thereby sputtered when the ions strike the surface. As a result, dielectric material deposited on the wafer surface is simultaneously sputter-etched to help keep gaps open during the deposition process, which allows higher aspect ratio gaps to be filled.
FIGS. 1A-1D illustrate, in more detail, the simultaneous etch and deposition (etch-dep) process described above. In FIG. 1A, a gas mixture of silane (SiH4), oxygen (O2), and an inert gas such as argon (Ar) begins depositing SiO2 on the surface of a wafer 100 for filling a gap 110 between circuit elements 120. As SiO2, formed from the SiH4 and O2, is being deposited, charged Ar and other charged ions impinge on the SiO2 or dielectric layer 125, thereby simultaneously etching the SiO2 layer. However, because the etch rate at about 45xc2x0 is approximately three to four times that on the horizontal surface, approximately 45xc2x0 facets 130 form at the corners of elements 120 during the deposition process, as shown in FIG. 1B. FIGS. 1C and 1D show the process continuing to fill gap 110 with simultaneous etching and deposition of SiO2.
In FIGS. 1A-1D, the etch/dep ratio, defined as the ratio of etch rate to deposition rate, is optimized such that facets 130 remain at the corners of circuit elements 120 throughout the HDP deposition process. However, as shown in FIG. 2A, if the etch/dep ratio is decreased, facets 130 begin moving away from the corners of elements 120, and cusps 210 begin to form around the entry or opening of gap 110. Cusp formation is due in part to some of the etched SiO2 being redeposited on opposing surfaces through line-of-sight redeposition, even though most of the etched SiO2 is emitted back into the plasma and pumped out of the reaction chamber. This redeposition increases as the distance between opposing surfaces decreases. Therefore, as facets 130 move away from the corners of elements 120, the line-of-sight paths are shortened, resulting in increased sidewall redeposition. At a certain point in the process, cusps 210 will meet and prevent further deposition below the cusps. When this occurs, a void 220 is created in dielectric layer 125, as shown in FIG. 2B. Thus, cusp formation creates reentrant features, i.e., the width at the entry to the gap is smaller than the width at the bottom of the gap, which makes void-free gap-filling harder to achieve. The likelihood of creating voids is increased when elements 120 are reentrant before the gap-fill process begins.
On the other hand, if the etch/dep ratio is increased, as shown in FIG. 3, the etching component can etch or xe2x80x9cclipxe2x80x9d material from the corners of elements 120, thereby damaging elements 120 and introducing etched contaminants 310 into dielectric layer 125.
By optimizing the etch/dep ratio, gaps with aspect ratios of up to about 4:1 and widths as low as 0.15 xcexcm can be filled without voids. However, as shown in FIG. 4, filling higher aspect ratio gaps and/or narrower widths results in voids 410 due to cusps 420 prematurely closing the gaps even if the etch/dep ratio is optimized. As discussed above, this is due mainly to the shortened line-of-sight path between opposing sidewalls. Cusp formation at the entry region of high aspect ratio gaps and narrow widths to be filled cannot be totally eliminated because sputtering and redeposition reactions are inherent to the physics and chemistry of the HDP CVD process. If the etch rate is increased to keep the gaps open longer, undesirable corner clipping can occur.
Therefore, with circuit densities increasing, a method is desired to fill higher aspect ratio gaps with narrow widths and gaps between reentrant elements without the problems discussed above with current HDP deposition processes.
In accordance with the present invention, a high aspect ratio gap-fill process uses a high density plasma (HDP) deposition process with a sequence of deposition and etching steps, where the etching steps utilize hydrogen (H2) to chemically etch the deposited material.
In one embodiment, gap-fill material, such as silicon dioxide, is deposited in a gap with a deposition process in a first step of the HDP process. Before the entry to the gap closes, the deposition step is interrupted to prevent void formation within the gap. In the next step, the overhang or cusp is removed by chemical etching using H2 (i.e., in a hydrogen-based plasma). The etching can be performed on an unbiased and unclamped wafer, in which case argon (Ar) gas can also be used, or with a bias HF power applied in which Ar is not used. Before the corners of the elements forming the gap are exposed from the etch step, the etch step is stopped to prevent corner clipping. Since the thickness of the material deposited at the entry region of the gap is lower than that at the bottom of the gap, the aspect ratio of the gap at the end of a deposition/etching cycle (deposition step followed by an etch step) is typically lower than the initial or previous aspect ratio. The deposition and etch steps can be repeated until the resulting aspect ratio is low enough to allow void-free gap-fill with a deposition step or a normal HDP CVD process. In principle, the overall process consists of 2n+1 steps, where n is a positive integer.
The etching steps utilize hydrogen. However, because hydrogen is an ineffective sputtering gas (i.e., due in part to its low weight), the etching is primarily due to a chemical reaction (SiO2+2H2xe2x86x92 greater than SiH4+O2). The etch rate increases with the LF power (or wafer temperature). Etching using this chemical reaction allows accurate control of the etch rate (due in part to a much lower etch rate than with conventional fluorine-based etch processes), a clean etching process (with no solid residual material), and high degrees of repeatability.
Throughput is also increased because the entire gap-fill process is performed in a single process chamber, instead of separate deposition and etch chambers. Etch/dep ratio is varied and transitions from deposition to etching steps are effected by changing the gas mixture chemical composition, the power supplied to the reactor, the chamber pressure, and/or the wafer temperature.
Accordingly, this invention accomplishes void-free gap-fill for gaps having high aspect ratios ( greater than 3.5:1) and small openings ( less than 0.13 xcexcm) through use of a composite multi-step HDP-CVD process using hydrogen in a chemical etch process.
This invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.